Programmable logic devices, such as for example a complex programmable logic device, are well known and are employed in numerous types of applications. A complex programmable logic device (CPLD) typically includes a number of monolithic and independent logic blocks interconnected by a global or centralized routing structure. One example of such a device is shown and described in U.S. Pat. No. 6,184,713, which is incorporated herein by reference in its entirety.
For example, FIG. 1 illustrates a block diagram of a conventional CPLD that includes a routing structure 100 and logic blocks 102 (sixteen independent logic blocks 102), with each logic block 102 having 16 macrocells and receiving 36 inputs from routing structure 100. The architecture of the logic block and of the routing structure (or interconnect) are two significant factors that determine the density, performance, and scalability of a CPLD.
As an example, a logic block architecture may include a programmable AND array to assist in providing AND-OR product term based logic (sum of products). The AND array generally has a large number of fuses, such as for example 2 (N)(M)(P) fuses, where “N” is the number of inputs to the logic block, “M” is the number of macrocells in the logic block, and “P” is the average number of product terms per macrocell. One drawback of this logic block architecture is that the number of fuses generally required (i.e., array fuse density or array fuse count) increases rapidly for higher density CPLDs with wide input logic blocks. Thus, smaller logic blocks tend to be more area efficient in terms of the number of fuses that are required for the AND array for a given number of macrocells.
A logic block may be measured in terms of its logic width capability (number of inputs) and its logic depth capability (number of product terms). Generally, a CPLD logic block has a fixed input width and a fixed number of product terms. Consequently, logic functions requiring more inputs or more product terms than are available from the logic block typically must be routed through the routing structure numerous times. This results in reduced performance and contributes to congestion in the routing structure.
As noted above, a CPLD routing structure architecture typically includes a centralized or global routing structure, which attempts to emulate to some extent a full cross-point switch to route various signals (e.g., macrocell feedback signals, input/output (I/O) feedback signals, or dedicated input signals) to appropriate logic blocks within the CPLD. As an example, a typical CPLD utilizes a multiplexer-based routing scheme to maximize speed while minimizing signal blocking (i.e., maximize routing capability). Each logic block generally receives all of its inputs from the routing structure via an associated, independent, and separate single-level multiplexer-based structure.
An interconnect fuse density associated with this routing structure is affected by the number of inputs to the logic block and the associated multiplexer structure. Generally, logic blocks having more inputs tend to be more interconnect efficient in terms of circuit area than logic blocks having fewer inputs, because there can be relatively fewer multiplexers and fewer interconnect fuses.
Because of the limitations noted above, CPLDs having small logic blocks (e.g., logic blocks with narrow inputs, such as for example 36 inputs that are typically associated with low density devices) are difficult to scale to higher densities, because of the poor interconnect efficiency (e.g., high interconnect fuse density) associated with the smaller logic blocks. On the other hand, CPLDs having large logic blocks (e.g., logic blocks with wide inputs, such as for example 68 inputs that are typically associated with high density devices) are difficult to scale to higher densities, because of the poor array efficiency (e.g. high array fuse density) associated with the larger logic blocks. Furthermore, logic block architectures having fixed logic width and/or depth have limited flexibility and may contribute to routing congestion. As a result, there is a need for an improved logic block architecture that may also provide the array efficiency associated with small logic block architectures and the interconnect efficiency associated with large logic block architectures.